Fixed Hardware Implementation using Built-In Generation of Functional Broadside Tests

Considering full-scan circuits, incompletely-specified tests, or test cubes, are used for test data compression. When considering path delay faults, certain specified input values in a test cube are needed only for determining the lengths of the paths associated with detected faults. Path delay faults, and therefore, small delay defects, would still be detected if such values are unspecified. The goal of this paper is to explore the possibility of increasing the number of unspecified input values in a test set for path delay faults by un specifying such values in order to make the test set more amenable to test data compression. Functional broadside tests are two-pattern scan based tests that avoid over testing by ensuring that a circuit traverses only reachable states during the functional clock cycles of a test. Experimental results indicate that significant numbers of such values exist. The proposed procedure un specifies them gradually to obtain a series of test sets with increasing numbers of unspecified values and decreasing path lengths. Experimental results also indicate that filling the unspecified values randomly (as with some test data compression methods) recovers some or all of the path lengths associated with detected path delay faults. The procedure uses a matching of the sets of detected faults for the comparison of path lengths. On-chip test generation has the added advantage that it reduces test data volume and facilitates at-speed test application. Here we are using modelsim6.4b and Xilinx ISE10.1 software tools for simulation and synthesis purpose.